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Hi Everyone,
I am thinking using PLL for clock derivation,but I have a problem for PLL inputs.There are 11 inputs for PLL and I wanna use multiplexer (created in FPGA) before PLL to select one of them as a input for PLL.but As I see PLL don't accept multiplexer output as input. I think I have to route Muxtiplexer output to FPGA output and then , I have to take it as a input from another FPGA
pin.So,I can use this signal for PLL input. but I don't want to waste FPGA pins.
Do you any idea How can I use multiplexer outputs for PLL inputs ? If you share your ideas ,I really appreciate this.
Thanks in advance
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The PLL ref input must be clean signal relative to PLL requirements. You can use one ref clock into a PLL with multiple outputs then insert a clock mux afterwards on various PLL outputs
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