Input port INCLK[0] of PLL is driven by OUTCLK output port of Clock control block type node.

Thank you for your reply. I'd like to describe my scenario more clearly at first. The external clock is connected to the dedicated clock pin, then it is directly connected to the PLL in my code. The OUTPUT pin of the PLL is feed to the global clock network, so it is the PLL to drive the GCLK network.

My purpose is to remove CLKCTRL module instead of changing its location by using the assignment "Global Signal CLKCNTRL location". This is because there was no CLKCTRL module between the dedicated clock pin and PLL input pin when this project was running on Quartus 9.0 with Cyclone III. This CLKCTRL module appeared when the whole project was migrated to MAX10 chip with Quartus 18.1 Lite currently. Therefore, I would be appreciated if there is a solution that can eliminate the CLKCTRL in the clock path which makes the design the same as the original one.