Occasional Contributor
Regular ContributorHi,
When driving the PLL using the GCLK network, the input and output delays might not be fully compensated in the Quartus Prime software.
Try by giving timing constrains and PLL Compensation assignments using the Assignment Editor(Assignment Name->Global Signal CLKCNTRL location). Which will eliminate the warning.
Checked it using PLL In source-synchronous compensation mode, In zero-delay buffer mode
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Regards
Anand
Occasional ContributorThank you for your reply. I'd like to describe my scenario more clearly at first. The external clock is connected to the dedicated clock pin, then it is directly connected to the PLL in my code. The OUTPUT pin of the PLL is feed to the global clock network, so it is the PLL to drive the GCLK network.
My purpose is to remove CLKCTRL module instead of changing its location by using the assignment "Global Signal CLKCNTRL location". This is because there was no CLKCTRL module between the dedicated clock pin and PLL input pin when this project was running on Quartus 9.0 with Cyclone III. This CLKCTRL module appeared when the whole project was migrated to MAX10 chip with Quartus 18.1 Lite currently. Therefore, I would be appreciated if there is a solution that can eliminate the CLKCTRL in the clock path which makes the design the same as the original one.
Regular ContributorHi,
Can you share the project ?
So that I can replicate the scenario.
Regards
Anand
