input pin to clock dff

Hello and thank you very much for your email
Sorry for the delay in my response.
Let's say that I partially manage to advance my design.
After a compilation my design works, then after another modification and compilation my design does not work anymore.
When the design was simple it worked well. Currently the design is becoming complex, about 85% of the FPGA gates are used. I also watch the compiltation time which increases with the complexity of the design. My computer is not fast, it takes patience.
The FPGA I am using is an EP3-C5 / 10.
In my board I use a 33MHz oscillator supplied with 3v3.
It is connected to the clock0 pin of the FPGA via a 33 Ω series resistor. To obtain a multitude of frequencies I used a simple divider counter which divides by 24 the clock of the oscillator.
I also use a PLL but the function which is fed by the signals of this PLL does not work.

I have read on various forums and documentation that clocks and signals should be synchronous.
Would there be a tutorial in French which simply explains the management of clocks and signals.
Is this synchronization valid for low frequency signals for example a few hertz at 5 kilohertz ?

Thank you for your understanding.

Regard