Input decay and state machine deadlock

Missing synchronization of asynchronous inputs must generally be expected to cause a state machine to get stuck in illegal states. As already mentioned, the synthesized logic ignores any unused respectively illegal states and thus don't necessarily recover from them.

Besides correct synchronization, which is recommended anyway, "safe" state machine encoding will reliably prevent locking in illegal states. It can be specified per FSM defintion by synthesis attributes:

// Safe State machine in Verilog
reg  my_fsm /* synthesis syn_encoding = "safe" */;

-- VHDL
TYPE STATE_TYPE IS (s_idle, s_sync1, s_sync2, s_sync3, s_data, s_check);
ATTRIBUTE syn_encoding : STRING;
ATTRIBUTE syn_encoding OF STATE_TYPE : TYPE IS "safe";	
SIGNAL state  : STATE_TYPE;