inout line undefined

Hello,

Here is the code that is confusing me. This is not the whole program, just a component.

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Serial_Communication is

Port ( i_CLK, i_CLKx2, i_EN, i_RD : in STD_LOGIC;

i_ADDR : in STD_LOGIC_VECTOR(6 downto 0);

io_DATA : in STD_LOGIC_VECTOR(15 downto 0);

io_SD : inout STD_LOGIC;

o_SEN, o_SCLK, o_DONE : out STD_LOGIC);

end Serial_Communication;

architecture Behavioral of Serial_Communication is

component CLK_Interrupt is

Port ( i_CLK, i_interrupt, i_idle_state : in STD_LOGIC;

o_CLK : out STD_LOGIC);

end component;

signal clk : std_logic := '0';

signal clkx2 : std_logic := '0';

signal sclk_interrupt : std_logic := '1';

signal clk_e : std_logic := '0'; -- early clk

signal clkx2_e : std_logic := '0'; -- early clkx2

signal clkx2_d : std_logic := '0'; -- delayed clkx2

signal sen : std_logic := '0';

signal o_sd : std_logic := '0';

signal i_sd : std_logic := '0';

signal tristate : std_logic := '0';

signal done : std_logic := '0';

begin

clk_e<=i_CLK;

clkx2_e<=i_CLKx2;

clk<=clk_e after 15ns;

clkx2<=clkx2_e after 15ns;

o_SEN<=sen;

o_DONE<=done;

V1: CLK_Interrupt port map (

i_CLK => clk,

i_interrupt => sclk_interrupt,

i_idle_state => '0',

o_CLK => o_SCLK);

process(clkx2, i_EN)

variable count : integer := 0; -- clkx2 counter

variable run : boolean := false;

begin

if clkx2'event and clkx2='1' then

if i_EN='1' then

run:=true;

end if;

if run=true then

count:=count+1;

else

done<='1';

count:=0;

end if;

if count=1 then

done<='0';

o_sd<='0';

tristate<='0';

elsif count=2 then

o_sd<=i_RD;

sen<='1';

elsif count=3 then

sclk_interrupt<='0';

elsif count<18 then

o_sd<=i_ADDR((17-count-(17-count)mod 2) /2);

elsif count<50 then

if i_RD='0' then

o_sd<=io_DATA((49-count-(49-count)mod 2) /2);

else

end if;

elsif count=50 then

if i_RD='0' then

o_sd<='0';

else

end if;

elsif count=51 then

sclk_interrupt<='1';

sen<='0';

elsif count=52 then

done<='1';

run:=false;

count:=0;

end if;

end if;

end process;

clkx2_d<=clkx2 after 15ns; -- makes sure the o_sd value is set before it is given out to io_SD

process(clkx2_d, tristate)

begin

if clkx2_d'event and clkx2_d='1' and tristate='0' then

io_SD<=o_sd;

end if;

end process;

end Behavioral;

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When I simulate my entire program the io_SD inout line is undefined whenever the i_EN line is '0'. If i_EN='1' then all signals are what they should be. Once the component, that is driving this one, sets i_EN to '0' simulation just ends. Changing the simulation run time does not work, it simply ends after i_EN='0'. If I start off with i_EN='0' then simulation run time is again a constant (15ns) and the io_SD is labeled "U", meaning undefined.

I assumed that the simulator was buggy and tried programming the FPGA. The program did not work as expected.

Maybe I should also mention that I am using xilinx ise project navigator 10.1.03(nt) for coding in vhdl. The FPGA is Xilinx Spartan XC3S1200E.