Inferring a DDR Input

And just in case FPGA_GUY didn't make it totally clear... No, you can't infer the megafunction in any of the major synthesis tools right now (third-party or Quartus II) - it's not like memory or multiplier functions which tools can infer from code and map to the device hardware blocks. I think it might be possible in theory so who knows, the vendors might add it some time, but instantiating the megafunction is pretty easy so I doubt it's a priority.

The Altera docs actually list the functions can that be inferred... Check out "Recommended HDL Coding Styles" http://www.altera.com/literature/hb/qts/qts_qii51007.pdf. Page 2 in the current 7.0.0 version:

You must use megafunctions to access some Altera

device-specific features. You can infer or instantiate

megafunctions to target some features such as memory and DSP

blocks. You must instantiate megafunctions to target device

features such as LVDS drivers, phase-locked loops (PLLs),

transceivers, and double-data rate input/output (DDIO)

circuitry.