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I suppose your incoming signal is asynchronous to your processing clock. As such it will have a different propagation delay to each register in the state machine and in the end each of the state-machine registers may see a different level, and possibly clock in an invalid transition ending up in an undefined state.
So you have to synchronise this external input with a two-stage register chain to avoid this (and metastability) issue.
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Thanks for your answer.
The external incoming signal is really asynchronious with the Primary Clock...As I understand, I have to transfer the icoming signal through FF that's syncronised with Primary Clock?
I would like to add more details...
The x"00" state disappear when I determine one or more states that I am not using - spare states.
Instead of x"00", I see the last state but still missing the rising edge.
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