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Altera_Forum
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12 years ago

Incorrect printline by using different memory segments

Hi! I have a system with NIOS and several memory blocks, 2 x On-Chip, SDRAM and SRAM. All of them work well, as long as I use same memory for all segments (.heap, .data, .stack....). As soon a...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Does your FPGA meet all timing specs?

Have you tried running the Memory tests on the different segments?

There should be nothing wrong with what your are doing. But i've see memory failures do odd things.

Pete