Honored Contributor
Honored ContributorThank you both for the replies. There is indeed an issue with the DCLK signal. The high level has some serious ringing (basically no settling on the high level) and there is also a strange element just before the rise of the clock signal. I am getting a short pulse just before each rise of the clock. I'll have to get a snapshot of the signal off my oscope and paste it onto another post here, but it does look like I need to clean up this signal.
I do not have any external circuitry driving the DCLK signal. It is the FPGA that drives this signal though yes? The only circuitry going to the AS header is the diode to 3.3V rail and the 10pf cap to gnd, but the line goes straight from FPGA to EPCS. Would it be advisable at all to use a larger capacitor here? Thanks again for all the help, this certainly narrows down the problem. So for the SFL configuration, is the setup primarily done in Quartus tool to generate a .sof file for programming, and the circuit is just configured as I would for AS mode? My board has two headers, one which is set up for AS mode with the configuration device, and another which is for JTAG mode. So programming indirect JTAG mode, I'd assume that I would still connect my blaster to the header for AS mode yes? And then do the appropriate set up for the .sof file? Or am I way off track? Thank you, I'm learning a lot! Sorry if these are basic questions, I'm still very new to Altera tools and FPGAs. ~doddy
