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Altera_Forum
Honored Contributor
Honored ContributorIn my project, I want to receive the lvds data from a AD device.
In my project, I want to receive the lvds data from a AD device. The timing diagrams is showed below
http://www.alteraforum.com/forum/attachment.php?attachmentid=12137&stc=1 where, the clk is from fpga to ad ;the two channel data a and b , dco are from ad to fpga, they are the source synchronous interface.
the two channels data are interval separated. Besides, the data bits wide is 14. I want to use the lvds_rx to receive the data from the AD.But I don't know how to set the parameter of the lvds_rx. The frequency of the dco is 125MHz. And the type of the FPGA is EP2AGX65DF.
2 Replies
Altera_ForumHello 0932,
Please go through these pdf's for the design guidelines for implementing altlvds_rx megafunction, so that you get clear idea of how to set the parameter values for your design https://www.altera.com/en_us/pdfs/literature/an/an479.pdf https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altera_lvds.pdf https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altlvds.pdf- Altera_Forum--- Quote Start --- Hello 0932, --- Quote End --- I second this. Also, I highly recommend testing using a simulator that includes the altlvds_rx and PLL to make sure that you are getting the expected output given an expected stimulus.
