In essence what makes a signal or even Asynchronous in a digital design

A signal generated on a clock edge is synchronised to that clock. It will never be nicely following it as rtl simulation models it but will follow the edge by reg tCO plus routing delay . If then static timing is happy then that delay will be absorbed within one clock period such that next edge will sample the change. All the combinatorial clouds between registers are assumed generated by source register on its clock. Any offchip signal or signals from a different clock domain joining the cloud are asynchronous unless clocks are related.

Thus it is true that a clean rtl functional model plus passing timing is good indicator of actual hardware model success. One of the main pitfalls here is multicycle de-constraints and false paths since rtl model is not aware of them yet timing model is. If you are not sure about your deconstraints then you better do timing simulation model. With these deconstraints, the actual delay inserted may exceed one clock period.