In altera Transceiver, why some protocols need rate match fifo, some don't need?

The rate match fifo and associated logic allow you to interface to a single clock domain that is local to your board (coreclk). The rate matching is done by inserting or deleting skip characters to keep the data flowing without overflowing or underflowing the phase compensation fifo. This saves you from managing the frequency differences yourself.

If it allowed you to remove the rate match fifo, the phase compensation fifo (which is small) may not be able to handle the differences in frequency causing you to drop or repeat parallel data words.

There are more details about how it works in the different device handbooks. For example, http://www.altera.com/literature/hb/stratix-iv/stx4_siv52001.pdf (http://www.altera.com/literature/hb/stratix-iv/stx4_siv52001.pdf)