In altera Transceiver, why some protocols need rate match fifo, some don't need?

PCIe, XAUI and GIGE specifications respectively state a ±300 and ±100ppm clock frequency tolerance between the bit rates of the transmitter and receiver at the two ends of a link.

So, if you want your product to be PCIe, XAUI or GIGE compliant, you have to implement a compensation device such a FIFO otherwise you can't put "PCIe, XAUI... Ready !" on your advertisement...

From a more technical point of view, I am wondering, perhaps as you, how two system reference clocks may have a frequency difference as great as 600ppm total (1.5MHz worst-case frequency delta for a 2.5Gbps in PCIe !...). Nowadays, any basic of-the-shelf VCXO can offer for a few dollars at least a 100ppm frequency stability over a wide temperature range. So you can find a better quality product with a slight "catalog research" effort.

In the end, the reason behind is probably that parts implemented for consumer electronics (like crystal oscillators) have to be as cheap as possible and that their default/poor quality may be compensated by "software" (gateware in our case)...