Implementing Power operator

For a constant base, the valid exponent range is rather limited, e.g. 0 to 20 for base 3 and a 32 bit result. So it can be realized as a case structure. It needs 52 logic cells with a Cyclone III.

I also tried with an iteration, but the compiler apparently wasn't able to reduce the result completely, it ended with about 650 logic cells. You can also calculate a table at compile time and infer either ROM or fixed logic. But I don't know if this works with Verilog, no problem with Quartus and VHDL, however.