Implementing custom DDR controller in Cyclone SOC

Sorry I did not see that the white paper was for the FPGA not the SOC version. You definitely can't replace the dedicated HPS hardened memory controller. But some models of the Cyclone V SOC models have one or more hardened memory controller with phy to the FPGA. Shouldn't it be possible to use a customized soft memory controller with one of the hardened phys dedicated to the FPGA as described in the Cyclone V white paper I linked to?

If that is possible then you can connect your custom memory controller to the HPS via the h2f_axi_master as you said BadOmen. This can be up to a 128-bit interface compared to 64-bit for HPS to Hardened DDR controller. The maximum frequency is probably less. But I would expect you could get decent performance.