Implementing custom DDR controller in Cyclone SOC

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Hi,

I don't have any direct experience with this but based on this document www.altera.com/literature/wp/wp-01188-hard-memory-controller-cv.pdf (http://www.altera.com/literature/wp/wp-01188-hard-memory-controller-cv.pdf) it seems like it is possible. Specifically it states that the memory controller can be bypassed (Bottom of page 2). I would probably confirm this with Altera though.

The Altera Cyclone V SOC Development Kit would be a good board to try this on since it has dedicated DDR3 for the FPGA as well as a hard memory controller and phy for the FPGA.

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Thanks for the response. The white paper that you suggested is on cyclone V FPGA series not on cyclone V SoC FPGA series. I want the ARM cores interfaced with my custom DDR controller thru AXI and DDR talking to external DDR via DDR PHY. Do you feel this is achievable with cyclone V SX SoC FPGA kit? Please suggest me some tutorials on SoC design using ARM cores. I am finding it tough to get any tutorial unlike Xilinx :(