Implementing an asynchronous counter in a FPGA

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Anyway in your last post you talked of superposed pulses: in this case the method doesn't apply, since you'll miss the pulse edges whenever they merge

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I just wanted to give the width of the pulse that needs to be captured. The merge will be handled differently. That was not related to the discussion, that why I didn't give more details.

I am going to try it out, and I will give you feedbacks

Thank you

Damien