Implementing an asynchronous counter in a FPGA

search for n-bit counter verilog (or VHDL), lots of examples will flood to your search results.

It does not need to be a gray counter. It makes no difference for you. Any type of counter suffices your need.

If your incoming pulses are 10-20 ns, you could certainly use a synchronous counter, clocked by the system clock @ 100 MHz for example (125 MHz for better results).

You should be able to pass EMC issues, since this is a typical frequency many EMC-compliant devices are working with.