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Honored Contributor
Honored ContributorImplementing an asynchronous counter in a FPGA
I need to implement a 32-bit counter that counts random impulsions in a FPGA. The counter has to be asynchronous (or not?) for the following reasons: - low consumption - to latch the impuls...
Altera_ForumHonored Contributor
Honored ContributorWhat's the expected pulse frequency? I mean the minimum time spacing between a pulse and the following one?
Let this time be T, then you could afford a system clock frequency as low as 1/T: you can probably use the pulse itself as clock input to set a flip-flop and then you use the system clock to sample and reset it. So the counter part would be kept synchronous and you can use a common counter, without harassing with ripple clocks, Gray code and async logic.
