Implementing an asynchronous counter in a FPGA

What's the expected pulse frequency? I mean the minimum time spacing between a pulse and the following one?

Let this time be T, then you could afford a system clock frequency as low as 1/T: you can probably use the pulse itself as clock input to set a flip-flop and then you use the system clock to sample and reset it. So the counter part would be kept synchronous and you can use a common counter, without harassing with ripple clocks, Gray code and async logic.