Implementation a common tristate output for a tristate array

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do you have any code yet? and what language are you trying to use?

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Hello. I have some code about it in VHDL,but I am not sure of it. the code is following. Do you have a better code than mine?

Thanks alot.

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library ieee;

use ieee.std_logic_1164.all;

entity tristate_dr is

port( d_in: in std_logic_vector(7 downto 0);

en: in std_logic;

d_out:out std_logic_vector(7 downto 0)

);

end tristate_dr;

architecture behavior of tristate_dr is

begin

process(d_in, en)

begin

if en='1' then

d_out <= d_in;

else

d_out <= "ZZZZZZZZ";

end if;

end process;

end behavior;