Forum Discussion

New Contributor

5 years ago

Implement static RAMs using memory blocks of CycloneII EP2C5ST144C8N

Hi all, I bought a cheap Cyclone II EP2C5T144 Dev Board to start with FPGA.Since I'm not yet familar with Verilog and VHDL I'm doing design with Quartus II block diagram simply translating my Kica...

RichardT_altera

Super Contributor

5 years ago

The Cyclone II M4K memory blocks do not support asynchronous memory, though they do support a pseudo-asynchronous read operation where the output data is available during the same clock cycle as when the read address is driven into it.

You can refer to below document for further information.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc/cyclone_device_handbook.pdf#page=183

Forum Discussion

Implement static RAMs using memory blocks of CycloneII EP2C5ST144C8N

Recent Discussions

Question

Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?

1.8 V LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices

Avalon-ST configuration with Agilex 3 fails

Quartus Prime Pro 25.1 fatal error during fitter: Windows "Efficiency mode" required