image read in vhdl

I have changed the code like this:-

for 0 to 64 clocks output will be extracted and once clock pulses exceed 64 (i.e., count value exceeds 64) algorithm will start and values will be loaded into d.

---main code

package newtype is

type row_t is array(0 to 63) of integer;

type matrix_t is array(0 to 7, 0 to 7) of integer;

type approx_t is array(0 to 30) of integer;

end newtype;

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.newtype.all;

entity test is

port(input: in matrix_t;

clk: in std_logic;

output : inout row_t ;

d : out approx_t);

end test;

architecture arch of test is

signal matrix : matrix_t;

signal temp_row : integer;

signal i : unsigned(5 downto 0) := "000000";

signal row, col : unsigned(2 downto 0) := "000";

signal count : integer := 0;

signal limit : integer := 64;

signal n : unsigned(6 downto 0) := "0000000";

signal temp_approx : integer;

begin

process(clk)

begin

if rising_edge(clk) then

if count < limit then

temp_row <= input(to_integer(row), to_integer(col));

output(to_integer(i)) <=temp_row;

col <= col + 1;

if col = "111" then

row <= row + 1;

end if;

i<=i+1;

else

temp_approx <= output(2*((to_integer(n)))+2)-(1/2)*(output(2*((to_integer(n)))+1)+output(2*((to_integer(n)))+3)) ;

d(to_integer(n)) <= temp_approx;

n<= n+1 ;

end if;

count <= count + 1;

end if;

end process;

end arch;

but still d contains garbage