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Honored Contributor
Honored Contributorimage read in vhdl
i want to read an image (or preferably a matrix of size 8x8) pixel by pixel in one clock cycle(if rising edge then read one pixel in 2nd rising edge 2nd pixel)....thanks in advance
Altera_ForumHonored Contributor
Honored Contributoryou cannot multiply unsigned type and real type (0.5). Real type is not suitable for synthesis. Try /2 instead.
But I still think you have real issues with your architecture. It is very inefficient and written as if it was software. Why do you have to "waste" clock cycles? Also - what external interfaces are you using? I doubt there are enough pins to output an entire 8x8 array - so why not do the calcualtions serially? Have you drawn out your circuit on paper?
