--- Quote Start ---
For a start, this is never going to work. It looks like you're trying to write sofware. This is clearly not the full code as there are lots of things missing (like a process, architecture, etity etc).
So errors in your code: row_pixel is an array of length 1. Your for loop also never executes as you have 0 downto 3 (a null range).
I suggest you go back to the drawing board - literally. DRAW your intended circuit on paper before you write any VHDL. VHDL is a hardware description language. Not a programming language. Writing code like software will not work.
--- Quote End ---
---main code
package newtype is
type row_t is array(0 to 3) of integer;
type matrix_t is array(0 to 3, 0 to 3) of integer;
type row_pixel is array (0 to 0) of integer;
end newtype;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.newtype.all;
entity test is
port(input: in matrix_t;
clk: in std_logic;
output : inout row_t;
output1 : out row_pixel);
end test;
architecture arch of test is
signal matrix : matrix_t;
signal temp_row : row_t;
signal temp_row_pixel : row_pixel;
signal count : unsigned(1 downto 0) := "00";
--signal output: row_t;
--function to extract rows
function extract_row( m : matrix_t; row : integer) return row_t is
variable ret : row_t;
begin
for i in row_t'range loop
ret(i) := m(row, i);
end loop;
return ret;
end function;
--function to extract each pixels of a row
function extract_row_pixel(row1 : row_t; pixel : integer) return row_pixel is
variable ret_pixel : row_pixel;
begin
for i in 0 to 3 loop
ret_pixel(i) := row1(pixel, i);
end loop;
return ret_pixel;
end function;
begin
process(clk)
begin
if rising_edge(clk) then
temp_row <= extract_row( input, to_integer(count) );
count <= count + 1;
output <= temp_row;
temp_row_pixel <= extract_row_pixel (output, to_integer(count));
count <= count + 1;
output1 <= temp_row_pixel;
end if;
end process;
end arch;
---testbench
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
use work.newtype.all;
entity test_tb is
end;
architecture bench of test_tb is
component test
port(input: in matrix_t;
clk: in std_logic;
output : inout row_t;
output1 : out row_pixel);
end component;
signal input: matrix_t;
signal clk: std_logic;
signal output: row_t;
signal output1 : row_pixel;
constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;
begin
uut: test port map ( input => input,
clk => clk ,
output => output,
output1 => output);
stimulus: process
begin
input <= ((0,1,2,9), (3,5,6,10), (9,8,11,2), (9,7,1,6));
wait for 50ns;
stop_the_clock <= true;
wait;
end process;
clocking: process
begin
while not stop_the_clock loop
clk <= '1', '0' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;
end;
Honored Contributor
