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Altera_Forum's avatar
Altera_Forum
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15 years ago

If there is no output port in code, Why the project will use 0 LEs after compilation?

Hi!

Everyone,

Nowdays I meet a question , If there is no output port in code, Why the project will use 0 LEs after compilation?

For example;

This is a short code with output port:

------------------------------------------

module IF_CASE1(clk,rst,datain/*,dataout*/);

input clk;

input rst;

input [3:0]datain;

//output [2:0]dataout;

reg [2:0]dataout;

always@(posedge clk)

begin

if (rst==0)

begin

dataout<=0;

end

else

begin

if (datain<4)

dataout<=1;

else if (datain<8)

dataout<=2;

else if (datain<12)

dataout<=3;

else

dataout<=4;

end

end

endmodule

--------------------------------------------------

and the printscreen is below after compilation.

http://images.cnblogs.com/cnblogs_com/tdyizhen1314/257630/r_%e6%88%aa%e5%9b%be2.jpg

but if the project has output port , the result is different from above.

you can see the compilation message.

http://images.cnblogs.com/cnblogs_com/tdyizhen1314/257630/r_%e6%88%aa%e5%9b%be1.jpg

Can you make a distinction bewteen the two situlations in detail?

Thanks!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    If the design has no output, the synthesisor can remove all logic elements in the design because they serve no purpose.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Here is a simple case: assign B = A; assign C = B; Now assume that C doesn't get used anywhere in your design or hooked up to a pin, Quartus II will determine that there is no point keeping C. Now if A and B are not used anywhere else in your design then A and B will be removed since C is removed. If you are familiar with C code compilers the behavior is similar to the optimizations they do.