I would like to know how to constrain my SPI clock on a slave. The FPGA is running as a slave to a raspberri pi master. Is it a base or virtual clock?

Thank you, I had once looked at the above link. That is not my exact situation. In my case, the clock is generated in the raspberry pi and delivered to the FPGA. The FPGA is acting as a slave in my design. SCLK needs constraining in the FPGA. In the above link, the FPGA is acting a master. In the above link, they used create_generated_clock to define the spi clock. I do not think that is the right command when the clock is generated in the raspberry pi. I suspect I need to use a virtual clock for this case, please elaborate how to constrain the SPI click in the FPGA. Lets assume that the spi clock is 1 MHz, when data is sent.