I want to design FIR and IIR Filters...

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for FIR

low-pass filter, order 55, with a cutoff at 10 hz, 500 samples/second

IIR

order 1, attenuation at 22 db

the thing is that i don't know which implementation is the best for use in order to save resources

until now I only had thinking in use flip-flops, multipliers and adders, but I think that this needs a lot of LEs

also I haven't decided the number of bits for the coefficients

I have a cyclone II ep2c8q208c7 (8300 LEs, 18 18x18-bit multipliers) and I have already use around 15% of the LEs

there is another way for implement the filter?

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There are many different ways to implement filters.

At 500 samples per second your FPGA has many many clock cycles to perform calculations. You can use a single multiplier and RAM and implement the FIR.

The IIR should be able to be implemented with 2 (Butterworth) or 5 multipliers per second-order-section.

You should perform a bit accurate simulation using a FIR/IIR design tool to determine the filter parameters.

Cheers,

Dave