PCiam
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NurAida_A_Intel
Frequent Contributor
Frequent ContributorHi Sir,
As per my understanding, you want to place all your DDR signal in Bank 6 and move the RUP/RDN from Bank 5 to Bank 6 as well. Is this correct? Please let me know if I understand this correctly.
If my assumption correct, kindly please refer to below explanation about the RUP/RDN placement :
- Some DQS or DQ pins are dual purpose and can also be required as RUP, RDN, or configuration pins. A DQS group is lost if you use these pins for configuration or as RUP or RDN pins for calibrated OCT.
- You need to pick RUP and RDN pins in a DQS group that is not used for memory interface purposes.
- You may need to place the DQS and DQ pins manually if you place the RUP and RDN pins in the same DQS group pins.
Regards,
Aida
PCiamNew Contributor
New ContributorHi Aida,
you are right. My goal is to place all the DDR signals on bank 6 in order to use bank 5 with a different VCCIO.
The idea is to use the DQS1 group (pin M15, M14 and so on) and additional pin for the control signals and addresses. All the DQS2 group signals (K14, K15 ...) are free so, if I understood well, I can move the RUP and RDN signals from bank 5 in a couple of pin of DQS2 group and ay yhe same time I'll loose the DQS2 functionalities. Is this correct.
I'll send you a possible pinout in order to check if I understood well the constrain, in that file the orange row are referred to DQS2 signal group and the green row are not usable.
I thank you very much for the support.
Best regards
Pietro Ciammaichella
Il 11/05/2020 06:55 Intel Forums ha scritto:
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