I have not modified the VHDL output file (.vho) by removing the reference to the Standard Delay Format Output File (.sdo). So why am I getting this error?

It seems that you are missing the .sdo file.

Note that: Gate-level timing simulation of an entire design can be slow and should be avoided.

Gate-level timing simulation is supported only for the Arria II GX/GZ,Cyclone IV, MAX

II, MAX V, and Stratix IV device families.. Use Timing Analyzer static timing analysis

rather than gate-level timing simulation.

Ref:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-tp-simulation.pdf

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