I design a board with max10,and do not design the reset input for max10, how can I generate a internal reset ?

to intel engineer

the sys_clk is 200Mhz, and the initial value of the counter register is 30'd200_000_005 need about 1 second to count,

I want to know :

1) which implementation is better , ak6dn's(directly using the input clcok ) or mine ?

2)if using ak6dn's, and the pll has several output clocks, the asynchronously asserting and synchronously desserting must be done according to different clock domain,right ?​

3) what is the intel oppion about that whether a input reset pin should be used or not ?