I design a board with max10,and do not design the reset input for max10, how can I generate a internal reset ?

Can I use the locked output of pll to generate a reset signal for my design?

Yes , you can use it , but you have to be careful since when clock fails or skew or jitter or any issue related to the clock; PLL will lose it lock and it will reset your system.

what is the best reset mode for max10 ?

I am not following you , what you really menat by reset mode of max 10 ?

For my board,there is no input signal, how can I generate​ a internal reset ,can you give me a example for that ,or where I can find the reference?

Can you refer to your another post , I replied to that

https://forums.intel.com/s/question/0D50P00004YEdCR/i-do-not-have-the-input-reset-signal-from-the-outside-of-the-altera-fpgaand-want-to-generate-reset-internallycan-i-do-like-below-

Thank you,

Regards,

Sree