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Altera_Forum
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8 years ago

I can't modify a file in quartus after generated the QSYS system? Please Help.

I'm making a flash controller in FPGA. I wrote the principal controller code, and another file that works like a test bench (a counter that generates the write and read instructions with datas) I nam...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

If your test_reg register is not used in the design (i.e. not connected to a FPGA pin or used by another module to generate a signal on an FPGA pin) then the whole register will be optimized away by the quartus synthesizer. You should see a warning about this in the synthesizer log.