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What do you mean by "showing me the old values"? The signal names, or is it that when you look at the waves it seems that it is still the old logic that is in place?
If it is just the signal names, the ones that are not part of your design any more are shown in red, and you need manually to delete them and insert the new signals in the window.
If it is just the wave that looks the same, did you click again on "run analysis"? If you still see what looks like the old logic would generate, then it means that either your modified code wasn't used by quartus, or that it doesn't do what you think it did. In either case check with the RTL viewer what Quartus synthesized.
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I just opened the RTL viewer, I found out that after compilation the RTL viewer can update the name of the register (for example I modified from "comm_in" to "comm_in_test" and changed the value, The logic Tap II also update the name of the same register (it turns red the old register name "comm_in", so I delete and add a new node from the list: "comm_in_test"). Here gets crazy, the value of that register "comm_in_test" is the old value from "comm_in", I don't even understand where the system gets that value since it comes from a parameter, which I actually changed to a new number...
Going back to Quartus I added a simple logic and a register like this:
///////////////////////////////////////////////
parameter test_A = 8'b0001_1111;
reg [7:0] test_reg;
always@ (posedge clock_sink_clk or negedge reset_sink_reset) begin
if (~reset_sink_reset)
test_reg <= 0;
else
test_reg <= test_A;
end
////////////////////////////////////////////
Compiled and generated in qsys, I checked and the submodule of qsys has made the changes also.
Then I open the RTL viewer, I cannot find the new register in the design, RTL viewer did not register the new logic I added.
What do you think is happening, this problem is a real puzzle.
I'm including the files I'm using in verilog. The TOP file generate the signals for the flash controller file itself.
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