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NReddy's avatar
NReddy
Icon for New Contributor rankNew Contributor
7 years ago

I am finding short between VCC and GND pins of EP1K100QI208-2 IC very frequently..any idea what could be the reason...?

1. EP1K100QI208 -2 IC been used in some of my old design and some are getting programmed in first power up but when i assemble the board into unit and power on , observing regulator failure ( getting...
ChiaLing_T_Intel's avatar
ChiaLing_T_Intel
Icon for Contributor rankContributor
7 years ago

Hi,

Intel FPGA Reliability Report had stated clearly that we have performs comprehensive testing and manufacturing controls on all its products. Reliability Report Figure 1 shows a typical product manufacturing flow. Thus, the devices are leaving factory in good and working condition. All our devices are fully tested as good before shipped to customer. The purpose of production testing during manufacturing is to screen out bad units and the shorted to ground pins would not pass the open/short test.

The VCC pin short to GND issue is highly suspected caused by an EOS event. This may be caused during reflow or just by someone touching the device or board without discharging themselves. This issue are generally due to Electrical Overstress (EOS) issue.

Generally, there could be various possible root causes of EOS; for example as below:

  • Uncontrolled voltage surge on the power supply
  • Voltage spikes due to internal PCB switching
  • Voltage spikes due to an external connection such as capacitive charge on an external cable, inductive loads.
  • Poor grounding resulting in excessive noise on the ground plane.
  • Overshoot or undershoot during IO switching
  • ESD events that trigger a larger EOS event or cause damage that weakens the device making it more susceptible to future EOS events.
  • Latch-up events may result in EOS damage if the current is high or if it persists for an extended time period.

The EOS might be caused by someone accidentally touching the device or board without discharging themselves properly. As the FPGA devices are ESD sensitive, it should be handled accordingly. User is recommended to ensure that the device is handled in proper way as recommended in the device handling guideline. Please refer to Guidelines for Handling Intel FPGA at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an071.pdf

We do not have the data proven on which voltage for how long will cause the device failure but users are always recommended the voltage at the pin should not exceed absolute maximum ratings.

Thank you

Regards,

Chia Ling