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MGane2's avatar
MGane2
Icon for New Contributor rankNew Contributor
7 years ago

I am currently using a Altera FPGA (EP3C16F484C8N). I need to provide 1.2V to the VCCD_PLL and VCCINT pins. I would like to know the acceptable noise level (Vrms) to those pins.

Based on the Noise level of those pins (VCCD_PLL & VCCINT) I need to qualify the LDOs. In general, the LDO's have output noise voltage of 10 to 100 uVrms. I would like to know what is the specified...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi ,

As of now, Intel does not provide the nose level for VCCD_PLL and VCCINT , decoupling have to provided depends up on decoupling requirements.

Regards,

RS