HSMC Interface - Signaling at 3.3V

You are ignoring a simple fact. The I/O-voltage for a particular I/O-Bank is set in the hardware, not in the pin assignments. The pin assignments can a best select a legal I/O standard for a certain I/O bank. The Dev. Kit's reference manual lists the available I/O standards for HSMC connected pins, they are all 2.5V, as far as I see.

But there is no problem, cause another of your assumptions is also wrong. Most (all?) 3.3V CAN drivers can be driven reliably by 2.5V CMOS logic. For the receiver, the 2.5V FPGA input can be driven by 3.3V logic, if you provide a source sided series termination to avoid overshoots above the permitted input level. A resistive divider to 2,5V or a diode clamp circuit would be an even better solution.