Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

HPS2FPGA bridge throughput

Hi everybody, I am currently playing around with the Cyclone V SoC Development board. I have a QSys system running resembling the Golden system reference design apart from the fact that the h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi, Can you please help me with the 2x HPS2FPGA bridges throughput / max clock / c code example (full bridge)

I use the lightweight for now at 100 Mhz successfully, at 200Mhz bridge fails. Someone mentioned max 133Mhz.for bridge clock. What is the maximum for Cyclone V I7 device.

Except for the data width of the full bridge, can I clock the bridge faster than the lightweight bridge for better throughput?

Except for data width why is it better performance for full bridge?

Can someone please help and provide me a c code (bare metal) example how to setup the full HPS2FPGA bridge, and how to use it e.g. Accessing a qsys component (PIO, memory ext). I do not find any examples on Web.

Thanks