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Altera_Forum
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12 years ago

HPS2FPGA bridge throughput

Hi everybody, I am currently playing around with the Cyclone V SoC Development board. I have a QSys system running resembling the Golden system reference design apart from the fact that the h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Dear Designer777,

I’m doing now a system that is quite similar to what you did a few months ago. We have managed to write to HPS’s SDRAM through hps2sdram bridge using modular SGDMA in the FPGA fabric. I have a counter that advances as long as the Avalon ready signal is asserted. I write this counter to SDRAM but after 63KB it stops and ready signal turns low. I defined descriptor.length = 0xFFFFFFFF;, tried different starting addresses, but the result is the same.

Could you please help me to understand how can I define the length in the SDRAM to which I’m writing?

Thanks,

A.