HPS2FPGA bridge throughput

One comment...

I have Cyclone V SoC experience almost a year.

The Quartus system has been well improved since 12.1, 13.01 ... 13.1 (HW/FW level).

However, it is sad but true fact that Altera could not provide at the moment any valuable reference designs (e.g. GHRD) to support the integration of FPGA-to-HPS bridges (opposite direction), and FPGA-to-SDRAM interfaces for memory bandwidth testing purposes. Released GHRD-s only integrates HPS-to-FPGA bridge or its LightWeight version. In most cases the information must be collected from different sources (this forum, rocketboard mail list, etc.). For an interesting component like the Address Span Extender has only a short Altera wiki entry :(

The only one Memory throughput SW test is in the BoardTestSystem (included in the Cyclone V SoC KIT package), but its source code has not been released yet (an SR sent about this without any success).

Unfortunately, their tutorials and reference designs are still not the same level as their IDEs.

Regards,

ZS.V.