HPS2FPGA bridge throughput

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Hi all,

I just want to add some feedback here.

I have now successfully integrated the modular SGDMA from BadOmen (http://www.alterawiki.com/wiki/modular_sgdma) on FPGA side and connected it as read master to the FPGA2SDRAM interface. I decided to use a FPGA DMA as I think I can get the highest performance this way (HPS DMA connected via L3, bandwidth to SDRAM controller must be shared with other peripherals).

My FPGA QSys bus logic allows a theoretical throughput of 320 MBytes/s to date (32 Bit Avalon MM IF on custom component @ 80MHz --> much room for optimization). With signal tap I see that the DMA is able to copy the data with a throughput of about 305 MBytes/s.

This looks really promising now :-)

Thanks again,

Volker

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Dear designer777 (http://www.alteraforum.com/forum/member.php?u=87612),

Ok. But what you wrote is the opposite direction e.g. FPGA_to_HPS_SDRAM_dedicated_interfaces (at max 6. channels) of this topic.

Combining FPGA-side DMA master peripheral to this dedicated interface sounds good.

I think "simple" FPGA_to_HPS_bridge has lower throughput.

When I first created a pilot QSys FW design with HPS_to_FPGA bridges, and an ARM swapped data between FPGA-side memory and on-chip (OCRAM) memory, I only measured 20-30 MBytes/sec (using SOCAL functions in BareMetal application). It is a poor performance.

Is the same performance of FPGA-to-HPS bridge and HPS-to-FPGA bridge?

Moreover, you mentioned ~ 80 MHz as clock freq = does it mean HPS-FPGA bridges clock freq driven from FPGA-side ALT_PLL?

Because, my former examination is that HPS-FPGA bridges clocks (e.g. h2f_axi_clock, h2f_lw_axi_clock, f2h_axi_clock etc.) can be used at most ~133 MHz clock speed. Have you any experience to set them properly?

Regards,

ZS.V.