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Altera_Forum's avatar
Altera_Forum
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7 years ago

HPS2FPGA bridge on DE0-Nano-SoC (5CSEMA4U23C6N) and GHRD

Hi! My device is DE0-Nano-SoC with GSRD and GHRD from System CD with minor changes. I implemented an Avalon-MM module and would like to access it throught HPS2FPGA by 128-bit bus. But I wa...
LTorr6's avatar
LTorr6
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7 years ago

Hi, can you tell me please what did you put on the HW_REGS_SPAN for the 128 bits bridge? Thanks