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Altera_Forum
Honored Contributor
7 years agoI've solved the problem!
First of all, the AXI data is plased where it should be: at 0xC0000000 offset. The readdata width of the Avalon MM module is truncated to 32 bits so it should be 32 bits to not been truncated. The test module just output the requested address as the readdata value:
module MY_AVALON_MEMORY(clk, resetn, readdata, address);
input clk;
input resetn;
input address;
output readdata;
assign readdata = address;
endmodule
Below are the most important parts of C program to print this: # define ALT_FPGASLVS_OFST ( 0xC0000000 )
...
void *virtual_base;
int fd;
fd = open( "/dev/mem", ( O_RDWR | O_SYNC ) );
virtual_base = mmap( NULL, HW_REGS_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd, ALT_FPGASLVS_OFST );
void *mem_addr;
void *mem_max;
uint32_t v;
mem_addr = virtual_base + ( ( unsigned long )( MY_MEMORY_0_BASE )); //This two constants are taken from the header which is generated by the generate_hps_qsys_header.sh
mem_max = virtual_base + ( ( unsigned long )( MY_MEMORY_0_END ));
while (mem_addr < mem_max) {
v = *((uint32_t *) mem_addr);
printf("%08X\t%08X\n", (unsigned int) mem_addr, (unsigned int) v);
mem_addr += sizeof(uint32_t);
}
close( fd );
The result are two pretty nice columns full of data:
72E19000 00000000
72E19004 00000001
72E19008 00000002
72E1900C 00000003
72E19010 00000004
72E19014 00000005
72E19018 00000006
72E1901C 00000007
72E19020 00000008
72E19024 00000009
72E19028 0000000A
72E1902C 0000000B
72E19030 0000000C
72E19034 0000000D
72E19038 0000000E
72E1903C 0000000F
72E19040 00000010
72E19044 00000011
72E19048 00000012
72E1904C 00000013
72E19050 00000014
72E19054 00000015
72E19058 00000016
72E1905C 00000017
72E19060 00000018
72E19064 00000019
72E19068 0000001A
72E1906C 0000001B
72E19070 0000001C
72E19074 0000001D
72E19078 0000001E
72E1907C 0000001F