HPS DDR3 in Cyclone V

Yes, the HPS SDRAM parameters aren't manifested in the rbf (so does most HPS parameters such as HPS PLL counter settings, HPS Pin Mux, etc). One important thing that do manifest in the rbf is the availability of the HPS-FPGA bridges (and the IPs connected to them). For example, if you remove the HPS-FPGA bridges in your design and reprogram the FPGA part only, the HPS doesn't know that the bridges are no longer visible - thus attempt from HPS to access the FPGA memory space will result in hang.

Then, there're also other signals such as FPGA-HPS interrupts, FPGA-HPS resets, etc. If you do use these signals then yes, you need to make sure that the FPGA rbf and HPS related files (bootloader, device tree) are updated.