Forum Discussion
Altera_Forum
Honored Contributor
14 years agoClock recovery has prerequisites on the protocol and hardware side. You need a respective data coding, e.g. 8b10b and a hardware with CDR capabilities. Gigabit transceivers have it, newer Arria and Stratix hardware SERDES units have a software CDR feature. With Cyclone III and newer, clock from data recovery can be implemented using the PLL dynamic phase shift option, at least for moderate data rates. It should work at 270 MBPS.