how to usethe dual port ram when reading and writing on the same moment?

The 'problem' is that the fpga timings don't allow for the data to propogate through the memory block - doing do would reduce Fmax significantly.

So during the clock cycle the output value from the memory changes from 'old data' to 'feed through of new data'. What the reading hardware sees depends on the propogation delays between the memory cell and the final latch.

Remember also that different bits of a word are likely to come from different memory blocks - so see different propogation delays.

M9K blocks definitely give random patterns when fed with two copies of the same clock and without OLD_DATA selected.