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Honored Contributor
Honored ContributorHow to use PLL in Cyclone II FPGA
Hi all, I want to use PLL in my design. I used quartus II(v7.2) megafunction to genarate a PLL. simulation results were proper. but when i m downloading the design to Cyclone II(EP2C8Q208C8...
Altera_ForumHonored Contributor
Honored ContributorThe reset is active high and i have verified in simulation also. PLL locked output is also taken to a pin. In simulation the PLL lock output was seen but after downloading to FPGA the locked output is not coming.
please help
