Altlvds IP core is a good choice but shift registers are easier to implement.
LTC2311 is a serial input ADC working with 5MSPS. Output of the ADC (SDO) should be connected to a differential input pair of the FPGA. SCK input of the ADC should be connected to output diff pair from the FPGA.
You also should study the timing characteristics of the ADC. I think the sclk can work up to 100MHz. Min clock you want is 16bits * 5M = 80MHz, if the 16-bit version of the ADC is used.
You should study the following time diagram carefully.
https://www.alteraforum.com/forum/attachment.php?attachmentid=12334