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Altera_Forum's avatar
Altera_Forum
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9 years ago

How to use LVDS on MAX10

Hi,

I'm relatively new to FPGAs and have only used these in dev boards like the BASYS3 and the BEMICRO MAX10. I need to interface the MAX 10 to an ADC(LTC2311) with serial LVDS. Could someone pls give me pointers/example code.

I have read several methods to do this including using shift registers or using the altlvds IP but I am not sure how I can do this. I really need some example code and help on how to start.

Any help would be appreciated.

Thanks.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Altlvds IP core is a good choice but shift registers are easier to implement.

    LTC2311 is a serial input ADC working with 5MSPS. Output of the ADC (SDO) should be connected to a differential input pair of the FPGA. SCK input of the ADC should be connected to output diff pair from the FPGA.

    You also should study the timing characteristics of the ADC. I think the sclk can work up to 100MHz. Min clock you want is 16bits * 5M = 80MHz, if the 16-bit version of the ADC is used.

    You should study the following time diagram carefully.

    https://www.alteraforum.com/forum/attachment.php?attachmentid=12334
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    Altlvds IP core is a good choice but shift registers are easier to implement.

    LTC2311 is a serial input ADC working with 5MSPS. Output of the ADC (SDO) should be connected to a differential input pair of the FPGA. SCK input of the ADC should be connected to output diff pair from the FPGA.

    You also should study the timing characteristics of the ADC. I think the sclk can work up to 100MHz. Min clock you want is 16bits * 5M = 80MHz, if the 16-bit version of the ADC is used.

    You should study the following time diagram carefully.

    https://www.alteraforum.com/forum/attachment.php?attachmentid=12334

    --- Quote End ---

    Thanks for your reply. So as for the shift registers, would you think I should implement the lpm_shiftreg megafunction? And would you have any suggestions in how to do this as far as programming goes? And yes, the SCK can go upto 105MSPS as per the datasheet.