How to use framebuffer when implementing line drawing algorithm in FPGA

Is this part of a homework and you are required to implement it this way? If so, if you only need to draw the one line, it seems like a framebuffer is overkill: your block could just receive a stream of pixels, overwrite pixels hit by the line, and passing through the unmodified pixels if not.

As far as your frame buffer approach in general: it sounds like read-modify-write and initializing the entire buffer to zero at the beginning of frame are not necessary. You should be able to write the framebuffer contents in one pass (pixels in the line are '1' and everything else is '0').

Depending on your frame rate / performance requirements, a FIFO may not be necessary: you can simply compute directly the address of the memory from the (x,y) coordinate of the pixel you are considering, issue the read, wait until it completes, modify it, issue the write, wait for it to complete, etc.

If you're doing this all as a part of a product development, Altera VIP IP suite has blocks for performing the mixing/overlay function, and you can either generate the line overlay from VHDL in a stream, or have it come from a buffer in RAM that you initialized with e.g. NIOS software.

If this block is the first of possibly many that you are creating, what you may want to consider is implementing a row buffer (cache) where your algorithms can directly address pixels in a given region (e.g. 8 or 16 lines) and a separate block manages the read/write of buffer contents between onchip M9K and off-chip SRAM/SDRAM.